1. Field of the Invention
The present invention relates to a circuit for driving a display unit such as a liquid crystal display (LCD) for a personal computer (PC), and in particular, a drive circuit of a display unit in which clock signals are increased in speed.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional general drive circuit of a display unit (hereinafter, referred to as a prior art 1). As shown in FIG. 1, a plurality of source lines 113 and a plurality of gate lines 116 are formed in LCD panel 105, and at the intersection of them, pixels using a TFT (a thin-film transistor) (not shown) as a switching device are arranged in a matrix form.
In FIG. 1, eight source driver LSIs (a display driver LSI) (hereinafter, referred to as a source driver) 103A through 103H to be connected to source lines 113 are arranged in a row, and four gate driver LSIs (hereinafter, referred to as gate drivers) 106 connected to the gate lines 116 are arranged in a column. These drivers comprise large scale integrated circuits (LSI).
Data is transmitted from PC (a personal computer) 100 to control circuit 101 of the liquid crystal module. Then, clock signals or the like are transmitted in parallel to the gate drivers 106 from the control circuit 101, a vertical synchronizing signal is transmitted to the first LSI of the gate drivers 106, and clock signals, digital image data signals, latch signals and others are transmitted to the source drivers 103A through 103H.
Then, at the point of time at which the TFT is turned ON by a positive voltage applied through the gate lines 116 from the gate drivers 106, a voltage applied through the source lines 113 from the source drivers charges liquid crystal load capacitance, and the TFT is turned OFF by a negative voltage applied through the gate lines 116 from the gate drivers 106, whereby the charged charge is held.
In a case where LCD panel 105 is an XGA (an extended Graphics Array) having 1024xc3x97768 pixels and a color type, the source lines 113 are 1024xc3x973=3072 lines, so that eight source drivers having 384 outputs become necessary. Due to the limitation of the semiconductor manufacturing device, the size of each chip is approximately 20 mm, and in the case of the XGA, eight to ten source drivers become necessary. In addition, when it is unnecessary to distinguish the eight source drivers, the drivers are just called source drivers 103A through 103H, and in a case where it is necessary to distinguish the eight source drivers, source drivers at 1st through 8th stages are called the first through eighth source drivers 103A through 103H, respectively.
As mentioned above, clock signals, digital image data signals, latch signals are transmitted to the source drivers 103A through 103H from the control circuit 101 to control each of the source drivers.
On the other hand, a start pulse signal (SP) is transmitted to only the first source driver 103A at the first stage shown at the left end in FIG. 1 among the source drivers 103A through 103H from the control circuit 101. Then, the first source driver 103A operates to shift by the clock signal, synchronously, and selects a bit number for sampling data. After the first source driver 103A reads-in data, the start pulse signal is transferred to the second source driver 103B at the next stage (at the next on the right) from the first source driver 103A. Then, the start pulse signal operates the second source driver 103B in the same manner as the operation for the first source driver 103A. Thus, as shown by the arrows in FIG. 1, the start pulse signal is transferred from first source driver 103A to the eighth source driver 103H in order. Such connection is called cascade connection, and this has been generally used.
Next, unlike the abovementioned case, an example of a connection between source drivers LSIs and a control circuit, which is not the cascade connection, is described. FIG. 2 is a circuit diagram showing a control circuit and source drivers in a display unit which are not cascade-connected. As shown in FIG. 2, in the case where a plurality of source drivers 203 are not cascade-connected, wiring for clock signals, digital image data signals, latch signals and others are connected from control circuit 201 to the source drivers 203 in parallel. Therefore, the timings of the transmission of these signals to the source drivers 203 can be directly controlled by the control circuit 201. Therefore, the start pulse signal (SP) becomes unnecessary. However, in such a method, the number of wires increases, so that this case is not realistic.
FIG. 3 is a timing chart showing signals inputted into the source drivers in the circuit of the display unit having a plurality of source drivers that are cascade-connected to each other in prior art 1 shown in FIG. 1. Latch signal (STB), clock signal (CLK), digital image data signals (D00 to Dxx), and polarity signal (POL) of FIG. 3 are inputted into the source drivers 103A through 103H in the same manner, however, the start signal (SP) of FIG. 3 show the timing chart of the start pulse signal to be inputted into the first source driver 103A at the first stage of FIG. 1. The period between one rise and the next rise of the start pulse signal shows the period of transfer (1 horizontal period) of the start pulse signal (SP) inputted into the first source driver 103A at the first stage to the eighth source driver 103H at the final stage of FIG. 1. As shown in FIG. 3, conventionally, the clock signals (CLK) to be inputted into the source drivers 103A through 103H always have clock pulses of a fixed frequency. When the digital image data signals (D00 through Dxx) are read into memories (not shown) inside the source drivers from the source drivers to which the start pulse signal has been transferred, and the source drivers 103A through 103H read the digital image data corresponding to 1 horizontal period, the data read in synchronization with the latch signals (STB) is latched, digital-analog converted, and then outputted.
Recently, as in prior art 1 shown in FIG. 1, the LVDS (the Low Voltage Differential Signaling) method has been used for data transmission from the PC to the control circuit 101 of the module. The advantage in the use of this LVDS method is that high-rate transfer is possible and the EMI (the Electro Magnetic Interference) can be suppressed since the transfer is carried out at a low amplitude voltage.
In the future, data transfer at a high-rate and at a low amplitude voltage also becomes important between the control circuit 101 and the source drivers 103A through 103H in the display module.
That is, the clock signals from the PC are currently at approximately 70 MHz in an XGA panel, however, the signals are at 160 MHz or more in a UXGA panel with 1600xc3x971200 pixels, and now, to double the frequency to be 320 MHz or more is being attempted.
However, in the abovementioned prior art 1 as shown in FIG. 3, the clock signal (CLK) always acts at a fixed frequency. Therefore, if the frequency of the clock signal increased, the action of the start pulse signal (SP) between the source drivers and transfer of the digital image data signals from the control circuit becomes unreliable.
The reason for this is because the transfer speed of the start pulse signal is limited to 200 MHz due to the use of CMOS interfaces between the source drivers. The internal functions of the source drivers stop until the start pulse signal is inputted. Even if the interfaces between the source drivers are improved, several nanoseconds (nsec) are required until the signals inside the source drivers, which have stopped, are started by the start pulse signal (SP). Therefore, the time for transferring the start pulse signal (SP) that is longer than the increased speed for the clock signal is required. However, the transfer time for the start pulse signal (SP), that is, the period from the input of the start pulse signal to the starting of the source drivers becomes impossible to secure in accordance with the increase in speed. Therefore, problems occur such that the digital image data signals are transmitted to the source drivers before the source drivers start operating. That is, the action of the start pulse signal (SP) to start the source drivers becomes unreliable.
A technology for correspondence with the clock signals at such a high frequency is disclosed in Japanese Patent Laid-Open Publication No.Hei.8-329696 (hereinafter, referred to as prior art 2). In prior art 2, a plurality of drivers are cascade-connected. The drivers include a multi-stage shift register, and lead-out outputs, which shift in order in synchronization with the input start signals, from each stage of the shift register. The drivers use the output start signals at the previous stage as input start signals, while the drivers generate signals, which are at a high level during a period corresponding to two periods of the clock signal, as output start signals by start signal generation circuits in response to the outputs from the previous stages before the final stage of the multi-stage shift register. Thereby, since the output start signals have times corresponding to the two pulse periods of clock signal, the drivers at the subsequent stages to which the output start signals are inputted can response at a desired timing even if the frequency of the clock signal increases. However, in the prior art 2, since the start signal generation circuits are provided for each driver, the unit becomes complicated.
It is an object of the present invention to provide a drive circuit of a display unit in which the transfer between the source drivers and the action for the source drivers of the start pulse signal are made reliable even if the speed of data transfer is increased in accordance with high speed clock signals.
A drive circuit of a display unit according to the present invention comprises a control circuit, source drivers and shift registers. Said display unit has transistors as switching devices, provided at intersections between a plurality of source lines and a plurality of gate lines intersecting the source lines, and display pixels arranged in a matrix form and controlled by the transistors. Image data outputted from the source lines is displayed in accordance with signals from the gate lines on the display pixels. The control circuit of the drive circuit generates a clock signal having a first clock pulse signal and a second clock pulse signal. The first clock pulse signal is generated in a reading period and the second clock pulse signal is generated in a transferring period. The reading period and the transferring period are alternately generated, and the frequency of the second clock pulse signal in the transferring period is lower than that of the first clock pulse signal in the reading period. The source drivers of the drive circuit are cascade-connected to each other at a plurality of stages. A start pulse signal is inputted into the source driver at the first stage, and the digital image data signals and the clock signals are inputted into the source drivers at each stage. The shift register provided in each of the source drivers transfers the start pulse signal to the source driver at the one-next stage per one transferring period so as to transfer the start pulse signals in order from the source driver at the first stage up to the source driver at the final stage. The source driver inputted into the start pulse signal reads the digital image data signal in the reading period.
In the driver circuit of the display unit according to the present invention, within the transferring period in which the clock signals to be inputted into the source drivers are low frequency clock pulse signals (a second clock pulse signal), the start pulse signal is transferred from one source driver to a source driver at the next stage, so that the start pulse signal can be securely transferred, and the period of time between the input of the start pulse signal and the starting of operation of the source driver can be reliably secured. Thus, since the control circuit generates clock signals that are low frequency clock pulse signals, the period of time from the input of the start pulse to the starting of the source driver""s read-in operation can be reliably secured.